Conventional power transistors are produced by connecting individual cells in parallel in the cell field. These individual cells are all identical in order to ensure reliable parallel operation. Currently, partially modified cell structures are used only in the edge area of the transistor, that is, between the cell field and the edge structure or between the cell field and the gate terminal/gate runner. The number of conductive individual cells for a power transistor is currently several thousand.
Frequently, trench MOSFETs are used for this purpose, which typically have low forward resistances and therefore low forward power losses. Trench MOSFETs have a gate electrode within the trenches, which is insulated from the surroundings by a gate insulator, usually a gate oxide. In trench MOSFETs it is necessary to ensure that the electric field intensity on the gate oxide remains within certain limits since otherwise undesired leakage currents or even the destruction of the gate oxide result.
To ensure reliable operation, approaches have been found that aim to reduce the electric field near the trenches by p-doped or effectively p-doped areas (in an npn layer sequence), for example by so-called p bubbles. In Takaye et al., Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs, p. 197-200 (2007), such p-type areas are introduced for a silicon-based trench MOSFET below the gate trenches, but are designed to be floating, that is, the p-type areas have no defined voltage potential. Nakamura et al., 2011 IEEE International Electron Devices Meeting, p. 26.5.1-26.5.3 (2011) describes a trench MOSFET based on silicon carbide (SiC), in which the p-type areas for field shielding are situated next to the trench and, in contrast to Takaya et al., Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs, p. 197-200 (2007), are connected to the source potential by a metallic coating. This connection is necessary for components based on silicon carbide (SiC) since otherwise, due to the minority carrier concentration being lower in comparison to silicon (Si) by orders of magnitude, a recharging of such p-type areas following their depletion takes very long and thus the switching behavior is markedly deteriorated. Another possibility for implementing a SiC trench MOSFET is described in European Patent No. EP2091083A2 (FIG. 1). In this instance, the p-type areas for field shielding are run orthogonally with respect to the trench lines. The contact is established directly on each trench, as in Takaya et al., Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs, p. 197-200 (2007). Another variant is described in U.S. Patent Application No. 2011/0121316 A1 for example (FIG. 1). In this instance, the p-type areas for shielding the electric field lie next to the gate trenches like in Takaya et al., Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs, p. 197-200 (2007). These p-type areas are likewise contacted in each cell.
The above-mentioned specific conventional embodiments all have in common that the contacted p-type areas for shielding the electric field lie completely or partially next to the gate trench. The contacts of the p-type areas are in these cases always established in situ. This creates an additional surface area requirement for the cell structure, which does not entail any additional increase in channel width. This increases the pitch measure of the transistor. The necessary surface area requirement for these p-type areas and for contacting the p-type areas in each individual cell adds up in accordance with the number of cells (several thousand per transistor).